1. Field of the Invention
The present invention relates to a semiconductor memory device and a redundancy method thereof, and is applied to, for example, a redundancy system and the like of a memory incorporated in a system LSI in a combined state.
2. Description of the Related Art
Heretofore, the capacity of a semiconductor memory device such as a static random access memory (SRAM) integrated into a system LSI tends to increase still more. On the other hand, in an SRAM or the like, redundancy for replacing a defective cell in a memory cell array with a redundant memory cell needs to be carried out. As a configuration for carrying out conventional redundancy, there is a configuration in which, for example, a spare row or the like including a redundant memory cell is provided in a memory cell array of an SRAM to be saved.
In the redundant memory cell of the spare row, a defective address of the SRAM (macro) to be saved, and replacement data thereof are stored. The defective address of the SRAM and the replacement data thereof are checked in advance by means of a tester, for example, in a functional test performed at the time of shipment.
Further, a row address included in externally input addresses (Add.) input to the SRAM is compared with a preprogrammed defective row address by an address comparator circuit provided in the SRAM. Subsequently, if the row address and the defective row address coincide with each other, then the row is replaced with any one of spare word lines (SWL) in the spare row to which any one of defective word lines (WL) corresponding to the defective row address is assigned.
However, in the conventional configuration, if it is tried to provide high-capacity redundancy, the area tends to increase.
This is because the defective word line (WL) of the cell array to be saved is replaced with one spare word line (SWL) as a unit, i.e., not with one memory cell as a unit, but with one word line (row) as a unit. With this configuration, not all the cells in the defective word line (WL) to be replaced are defective, and hence even cells which do not originally need to be replaced are replaced. Thus, all the cells connected to the word line (WL) are replaced, and replacement in units of one word (cell) cannot be performed.
For example, in the case of an SRAM provided with additional 64 spare rows for a memory cell array of 512 rows, the ratio of the area of the spare rows to that of the memory cell array is 12.5%. Further, even the ratio of the area of the spare rows to the entire SRAM (macro) area exceeds 10% leading to an area penalty. Thus, the area efficiency is remarkably low. As a result, when it is necessary to provide the high-capacity redundancy, the area efficiency is very low.
Furthermore, the spare rows and the address comparator circuit and the like constituting the redundancy are provided as hard intellectual property (IP) on the layout level. As a result, once the SRAM is designed, when, for example, it becomes necessary to obtain a macro in which the number of spare rows is reduced, and the area is also reduced due to an improvement in the manufacturing level of the factory, the time needed to redesign the spare rows tends to increase.
Examples of known documents relating to the invention of the present application are K. Pagiamtzis et al., “Content-Addressable Memory (CAM) Circuits and Architectures: A Tutorial and Survey”, IEEE J. of Solid-State Circuits., vol. 41, No. 3, pp. 712-727, March 2006, and H. Ito et al., “Pure CMOS One-time Programmable Memory using Gate-Ox Anti-fuse”, in CICC Tech. Dig., 2004, pp. 469-472H.